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. which will then cause the circuit conditions to be set up for operation. ZCS goes beyond ductile technology.1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming gate structures of a semiconductor device.
2. Description of the Related Art
Manufacturing of a highly integrated circuit (IC) requires miniaturization of various patterns. Among these patterns, the minimum pattern size for forming a gate electrode of a field effect transistor (FET) is substantially reduced.
Hereinafter, a conventional method of forming gate structures will be described in detail with reference to the attached drawings.
FIGS. 1A through 1D are sectional views sequentially showing a conventional method of forming gate structures.
As shown in FIG. 1A, gate trenches 11 are formed at a predetermined interval, on a semiconductor substrate 10 that is divided into a cell region and a peripheral region, by a conventional method. The gate trenches 11 are formed with a predetermined depth, using a first masking process in which an oxide layer (not shown) is entirely formed on the semiconductor substrate 10, and the first masking process is removed. In order to form a gate insulation layer, a first oxide layer 12 of a thickness of about 1000.ANG. is formed over the entire surface of the semiconductor substrate 10 by a conventional method. Thereafter, the first masking process is performed with a second masking process in which a polysilicon layer (not shown) is formed by a chemical vapor deposition (CVD) process on the first oxide layer 12 formed on the semiconductor substrate 10, and the second masking process is removed. Thereafter, the polysilicon layer is patterned to form polysilicon gate electrodes in the cell and the peripheral regions. The first oxide layer 12 formed between the polysilicon gate electrodes defines a gate dielectric.
Subsequently, as shown in FIG. 1B, the first oxide layer 12 located over the cell region is selectively removed to expose the semiconductor substrate 10, and thus forming a trench gate (for example, refer to the aforementioned gate trenches 11). However, the first oxide layer 12 on the peripheral region is thinned to a certain thickness to form a tunnel oxide layer over the tunnel region. Subsequently, as shown in FIG. 1C, a thin silicon oxynitride film (SiON) is formed over the
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